The present invention relates to a semiconductor integrated circuit having a self-test circuit.
Semiconductor integrated circuits (LSIs) are known which have a BIST (built-in self-test) circuit for conducting a self-test. Upon a start of a test, the BIST circuit generates test patterns and supplies those to a test subject circuit such as a memory circuit or a logic circuit. The BIST circuit judges whether the test subject circuit is defective or not by comparing data indicating test results of the test subject circuit with expected values.
As shown in FIG. 3, a test circuit disclosed in Patent document 1 includes transistors 5 and 6 whose one terminals are connected to each other. An enable signal 2 is input to the gates of the transistors 5 and 6, and input signals 3 and 4 are input to the other terminals of the transistors 3 and 4, respectively. The transistors 5 and 6 are turned on when the enable signal 2 becomes active. The input signals 3 and 4 are compared with each other in this state. Since the transistors 5 and 6 are wire-connected to each other, no current flows through the transistors 5 and 6 as long as the potentials of the input signals 3 and 4 are the same. But an abnormal current flows if the potentials of the input signals 3 and 4 are different from each other. The test circuit makes a failure/non-failure judgment on the basis of the value of the abnormal current.
As shown in FIG. 4, a memory module test circuit disclosed in Patent document 2 includes NAND gates 11 and 14, a NOR gate 12, a NOT gate 13, and a transistor 15. Each memory module has I/O ports (input/output terminals) for communization of a data input and a data output. A test result is also output from an I/O port by switching operation of the transistor 15. The communization of the terminals reduces the number of terminals.
[Patent document 1] JP-A-2000-088926
[Patent document 2] JP-A-4-010040
In the test circuit of Patent document 1, since the output terminals of the transistors 5 and 6 are short-circuited with each other, the transistors 5 and 6 may be broken by a flow-through current. Such breaking causes no problem because the test subject circuit is originally in failure. However, the above test circuit cannot be applied to a case that a memory that once produced a test result “NG” is tested again after being subjected to redundancy remedy to increase the yield. Furthermore, with the above test circuit, a failure analysis cannot be performed easily because a failure/non-failure judgment is made on the basis of an abnormal current flowing through the transistors 5 and 6.
In the test circuit of Patent document 2, since plural memory modules are bundled by means of the logic gates, the number of logic gates increases as the number of memory modules increases.